1. Field of the Invention
This invention relates to the digital filtering of an oversampled single bit data stream input. More particularly, it relates to an architecture for an improved sigma delta filter which performs a filtering function on a oversampled single bit stream input without DC transients.
2. Background of Related Art
Digital filters such as Infinite Impulse Response (IIR) filters have been implemented with sigma delta architectures operating at an oversampled rate. For instance, first order filter sections can be implemented with a denominator coefficient multiplying the single bit output from a sigma delta modulator in a feedback loop, and with a numerator coefficient multiplying the single bit input to the sigma delta modulator in a feedforward loop. In this configuration, both the feedback loop and the feedforward loop are added at an input summing node of the sigma delta modulator.
Further enhancements have been achieved to reduce noise. For instance, reduced noise has been achieved by passing only one minus the difference of the desired feedback coefficient through the sigma delta modulator.
Coefficients can be chosen to implement either high pass or low pass responses. In the case of a high pass filter response, an undesired effect of a decaying DC term in the signal spectrum is caused when both the pole and zero are close to the unit circle. In such a case, a less than desirable solution is to wait a sufficiently long enough period of time for the DC transient to die out. If the output signal were to be interpreted by a receiving device (e.g., at a telephone company from a customer premises device employing such an IIR filter), a wrong signal may be interpreted.
FIG. 3 shows the details of a conventional first order single bit filter 190.
In particular, in FIG. 3, a summing node 110 receives and sums an input to the sigma delta filter from gain module 100, a delayed feedforward term from coefficient module 104, and a feedback term output from a sigma delta modulator 120.
The xe2x80x9cG timesxe2x80x9d portion of the numerator of the transfer function of the sigma delta filter 190 is formed with a gain module 100, and the xe2x80x9c1 minusxe2x80x9d portion of the numerator of the transfer function of the sigma delta filter 190 is formed by a register value output from the feed forward term output from the a0 coefficient module 104. The register value output from the feed forward term coefficient module 104 is either added or subtracted at the input summing node 110, depending upon the delayed (i.e., nxe2x88x921) value of the single bit sample input to the sigma delta filter 190. The a0 coefficient module 104 is typically implemented using a simple adder/subtractor.
The xe2x80x9c1xe2x80x9d portion of the denominator of the transfer function of the sigma delta filter 190 is provided with the feedback to the summing node 110 directly from the sigma delta modulator 120 (through factor module 112). The xe2x80x9cb0xc3x97zxe2x88x921xe2x80x9d portion of the denominator of the transfer function of the sigma delta filter 190 is formed by the feedback paths.
Only a portion of the feedback coefficients are passed through the sigma delta modulator 120, the remaining portion being passed through the delay term 116. In FIG. 3, the sigma delta modulator 120 is a second order modulator designed with a delay of zxe2x88x921.
For the zxe2x88x921 term in the denominator, the output of the single bit sigma delta modulator 120 is multiplied by (1xe2x88x92b0) in the factor module 112, and subtracted at one input to the summing node 110. Multiplication in the factor module 112 is performed, e.g., by simply adding or subtracting register values which contain the partial feedback coefficients (1xe2x88x92b0). The remaining portion of the denominator coefficients, zxe2x88x921, is fed back and added at the first input to the summing node 110 prior to going through the sigma delta modulator 120.
The output from the delay term 116 is added at a second input to the summing node 110. The output of the a0 feed forward coefficient module 104 is subtracted at a third input to the summing node 110, and the gained input to the sigma delta filter 190 output from the gain module 100 is added at a fourth input to the summing node 110.
In order for a highpass filter configuration to be implemented, the numerator coefficient a0 must be greater than the denominator coefficient b0. However, when the denominator coefficient b0 is very close to 1, the term (1xe2x88x92b0) fedback through the sigma delta modulator 120 through the factor module 112 becomes very small. Consequently, with this small feedback value, the sigma delta modulator 120 takes a finite period of time to again reach steady state, with this delay manifesting itself as a decaying DC component. This decaying DC component forms a DC transient signal in the sigma delta filter 190. Unfortunately, the DC transient signal causes a significant delay until the output of the sigma delta filter becomes accurate. Thus, a DC transient signal in a filter is highly undesirable, particularly for a high pass filter.
There is thus a need for a digital filter architecture which is capable of overcoming the significant delays caused by DC transients in a digital filter, particularly in a sigma delta filter.
In accordance with the principles of the present invention, a digital filter comprises a summing node including at least one feedback input, and a feedback term. A mechanism switches between two sources of the feedback term. A first of the two sources is an output of the summing node, and a second of the two sources is a non-zero preset value.
A method of providing a digital data stream to a digital filter in accordance with another aspect of the present invention comprises providing a non-zero preset value as a temporary input to a feedback term. An output of the feedback term is summed in an input summing node to a digital filter. An output of the summing node is provided to the input to the feedback term.